Dynamic random access memory cell layout and fabrication method thereof

ABSTRACT

A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a memory cell of a semiconductor device, andmore particularly to a dynamic random access memory (DRAM) cell layoutfor arranging deep trenches and active areas and a fabrication methodthereof.

2. Description of the Related Art

A dynamic random access memory (DRAM) cell typically includes a memorycell coupled to a storage capacitor. Generally the storage capacitor isformed within a deep trench etched into a semiconductor substrate. Thestorage capacitor is accessed using an access transistor which allowscharge to be stored in the storage capacitor or retrieves charge fromthe storage capacitor depending on whether the desired action is a reador write function. For a buried strap type trench capacitor, dopantoutdiffusion near a wordline can cause a short channel effect in theaccess transistor channel, thus reducing subthreshold conduction andcausing a fail in retention time.

FIG. 1 is a conventional DRAM cell layout. Deep trench capacitors 10 aredisposed under passing wordlines 12. Access transistors 14 areelectrically coupled to storage nodes 16 of the trench capacitors 10through diffusion regions 18 which may be either a source or a drain ofthe access transistors 14. Diffusion regions 20 are electricallyconnected to bitline contacts 22 which connect to bitlines (not shown)to read and write to the storage nodes 16 through the access transistors14. Access transistors 14 are activated by the wordlines 12. Whenvoltage is applied to the wordlines 12, a channel below the wordline 12conducts and allows current to flow between diffusion regions 18 and 20and into or out of the storage node 16. Wordlines 12 are preferablyspaced across the smallest possible distance to conserve the layoutarea. The smallest possible distance is typically a minimum feature size“F”.

FIG. 2 is a cross-section along line 2-2 of FIG. 1. Elements of FIG. 2are labeled as described in FIG. 1. The storage nodes 16 are isolatedfrom a doped well 24 by a dielectric collar 26. A shallow trenchisolation (STI) 28 is provided over the storage nodes 16 to electricallyisolate the passing wordlines 12 formed above storage nodes 16. Thediffusion region 18 of the access transistor 14 is connected to thestorage node 16 through a buried strap (BS) 32 and a BS out-diffusionregion 30. Considering an overlay tolerance effect, a BS mergephenomenon easily occurs to cause a short channel effect in a channelregion 34 underlying a gate electrode 36 of the access transistor 14.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a DRAMcell layout and a fabrication method thereof to improve subthresholdconduction and retention time performance.

According to the object of the invention, a dynamic random access memorycell layout has a first gate conductor pair and a second gate conductorpair extending along a first direction, in which each gate conductorpair comprises a first gate conductive line and a second gate conductiveline. A bitline pair has a first bitline and a second bitline, whichextend along a second direction and intersect the gate conductor pairs.Corresponding to the first bitline, a first active area extends alongthe second direction to cross the first gate conductor pair.Corresponding to the second bitline, a second active area extends alongthe second direction to cross the second gate conductor pair. Eachactive area has a first deep trench and a second deep trench formed in asubstrate underneath the first gate conductive line and the second gateconductive line, respectively. A bitline contact is formed between thefirst gate conductive line and the second gate conductive line to beelectrically connected to the corresponding bitline. A commonsource/drain region is formed in the substrate between the first gateconductive line and the second gate conductive line to be electricallyconnected to the bitline contact. A first vertical transistor and asecond vertical transistor are formed overlying the first deep trenchand the second deep trench, respectively. Each vertical transistor has aburied strap out-diffusion region formed in the substrate adjacent toone sidewall of the deep trench.

DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawings,given by way of illustration only and thus not intended to be limitativeof the present invention.

FIG. 1 is a conventional DRAM cell layout.

FIG. 2 is a cross-section along line 2-2 of FIG. 1.

FIG. 3 is a DRAM cell layout of deep trenches and active areas accordingto the first embodiment of the present invention.

FIG. 4 is a cross-section along line 4-4 of FIG. 3.

FIG. 5 is a DRAM cell layout of deep trenches and active areas accordingto the second embodiment of the present invention.

FIG. 6 is a three-dimensional diagram of a vertical transistor accordingto the second embodiment of the present invention.

FIGS. 7A-7L are cross-sections of a fabrication method forabove-described deep trenches and vertical transistors.

DETAILED DESCRIPTION OF THE INVENTION

First Embodiment

FIG. 3 is a DRAM cell layout of deep trenches and active areas accordingto the first embodiment of the present invention. The DRAM cell layoutcomprises a plurality of gate conductor pairs P₁, P₂ and P₃ and aplurality of bitlines BL₁ and BL₂. Each of the gate conductor pairs P₁,P₂ and P₃ comprises a first gate conductive line GC₁ and a second gateconductive line GC₂ arranged parallel to each other. The gate conductivelines GC₁ and GC₂ extending along a first direction and the bitlines BL₁and BL₂ extending along a second direction intersect to define aplurality of DRAM cells. A first active area AA₁ is defined at theintersection of the second gate conductor pair P₂ and the first bitlineBL₁. A second active area AA₂ is defined at the intersection of thefirst gate conductor pair P₁ and the second bitline BL₂, alternatively,at the intersection of the third gate conductor pair P₃ and the secondbitline BL₂.

The first active area AA₁ extends along the first bitline BL₁ to crossthe first gate conductive line GC₁ and a second gate conductive line GC₂of the second gate conductor pair P₂, and comprises two verticaltransistors T_(1 and T) ₂, a common bitline contact BC and two deeptrenches DT₁ and DT₂. The first vertical transistor T₁ is formed on aregion where the first deep trench DT₁ is partially overlapped with thefirst gate conductive line GC₁. The second vertical transistor T₂ isformed on a region where the second deep trench DT₂ is partiallyoverlapped with the second gate conductive line GC₂.

The second active area AA₂ extends along the second bitline BL₂ to crossthe first gate conductive line GC₁ and a second gate conductive line GC₂of the first gate conductor pair P₁. Alternatively, the second activearea AA₂ crosses the first gate conductive line GC₁ and a second gateconductive line GC₂ of the third gate conductor pair P₃. The secondactive area AA₂ comprises two vertical transistors T₁ and T₂, a commonbitline contact BC and two deep trenches DT₁ and DT₂. The first verticaltransistor T₁, is formed on a region where the first deep trench DT₁ ispartially overlapped with the first gate conductive line GC₁. The secondvertical transistor T₂ is formed on a region where the second deeptrench DT₂ is partially overlapped with the second gate conductive lineGC₂.

FIG. 4 is a cross-section along line 4-4 of FIG. 3. For the first activearea AA₁, the first deep trench DT₁ and the second deep trench DT₂ areformed by etching a semiconductor silicon substrate 40, and a shallowtrench isolation structure STI is formed outside the first deep trenchDT₁ and the second deep trench DT₂ for isolating the first active areaAA₁ from the second active area AA₂. A first deep trench capacitor C₁and a second deep trench capacitor C₂ are formed at the lower portionsof the first deep trench DT₁ and the second deep trench DT₂,respectively. A first buried strap out-diffusion region BS₁ is formed inthe substrate 40 adjacent to one sidewall of the middle portion of thefirst deep trench D₁. The first buried strap out-diffusion region BS₁serves as a source/drain region of the first vertical transistor T₁, andprovides an electrical connection between the first vertical transistorT₁ and the first deep trench capacitor C₁. Similarly, a second buriedstrap out-diffusion region BS₂ is formed in the substrate 40 adjacent toone sidewall of the middle portion of the second deep trench D₂. Thesecond buried strap out-diffusion region BS₂ serves as a source/drainregion of the second vertical transistor T₂, and provides an electricalconnection between the second vertical transistor T₂ and the second deeptrench capacitor C₂. The first gate conductive line GC₁ partiallyoverlaps the upper portion of first deep trench DT₁ to serve as a gateelectrode of the first vertical transistor T₁. The second gateconductive line GC₂ partially overlaps the upper portion of second deeptrench DT₂ to serve as a gate electrode of the second verticaltransistor T₂. A common source/drain region S/D is formed in thesubstrate 40 between the first gate conductive line GC₁ and the secondgate conductive line GC₂. Thus, a first vertical channel region isprovided between the common source/drain region S/D and the first buriedstrap out-diffusion region BS₁, and a second vertical channel region isprovided between the common source/drain region S/D and the secondburied strap out-diffusion region BS₂. The bitline contact BC is formedoverlying the common source/drain region S/D and electrically connectedto the first bitline BL₁. Accordingly, the DRAM cell layout of thevertical transistors T₁ and T₂ and the deep trenches DT₁ and DT₂ canprevent deterioration of subthreshold conduction, thus improvingretention time performance.

Second Embodiment

FIG. 5 is a DRAM cell layout of deep trenches and active areas accordingto the second embodiment of the present invention. FIG. 6 is athree-dimensional diagram of a vertical transistor according to thesecond embodiment of the present invention. Elements similar to thoseshown in FIGS. 3 and 4 are omitted here.

The DRAM cell layout of deep trenches and active areas of the secondembodiment is substantially similar to that of the first embodiment,with the similar portions omitted herein. The different portion is theprofile of the overlapping region between the deep trench and thevertical transistor. In the first embodiment, on the overlapping regionbetween the deep trench and the vertical transistor, the sidewallprofile of the deep trench is a line. Comparatively, in the secondembodiment, on the overlapping region between the deep trench and thevertical transistor, the sidewall profile of the deep trench comprisesat least three edges. For example, a five-edge sidewall profile, such asa

-shaped sidewall.

Preferably, on an active area AA, the first deep trench DT₁ is partiallyoverlapped with the first gate conductive line GC₁, and the first deeptrench DT₁ comprises a

-shaped sidewall within the overlapping portion therebetween. Similarly,the second deep trench DT₂ is partially overlapped with the second gateconductive line GC₂, and the second deep trench DT₂ comprises a

-shaped sidewall within the overlapping portion therebetween. Therefore,the vertical channel region between the common source/drain region S/Dand the buried strap out-diffusion region BS becomes a multilateralstructure, viewed as a three-dimensional design, which can furtherimprove subthreshold conduction and retention time performance.

Third Embodiment

FIGS. 7A-7L are cross-sections of a fabrication method forabove-described deep trenches and vertical transistors.

In FIG. 7A, an array area I and a support area II are defined on asemiconductor silicon substrate 40. A p-type semiconductor siliconsubstrate 40 is described below for example. First, a pad layer 41 and areactive ion etching (RIE) method are employed to pattern a deep trenchDT in the substrate 40 within the array area I. Then, a deep trenchcapacitor 42 including a bottom electrode plate 44, a capacitordielectric 46 and an upper electrode plate 48 is fabricated at the lowerportion of the deep trench DT. Preferably, the bottom electrode plate 44is an n⁺-type diffusion region, the capacitor dielectric 46 is an ONO(oxide-nitride-oxide) stack structure, and the upper electrode plate 48is a first polysilicon layer with n⁺-type dopants. Next, in a collardielectric process, a collar dielectric layer 50 is formed on thesidewall of the deep trench DT. Next, a second polysilicon layer 52 withn⁺-type dopants and a third polysilicon layer 54 are formed in the deeptrench DT. Next, a thermal diffusion process is employed to make then⁺-type dopants diffuse through the third polysilicon layer 54 into thesubstrate 40, resulting in a buried strap out-diffusion region 56 in thesubstrate 40 adjacent to the third polysilicon layer 54. Next,deposition and etching are used to form a top isolating layer 58 on thethird polysilicon layer 54.

In FIG. 7B, an anti-reflective coating (ARC) layer 60 is formed in thedeep trench DT, and a first photoresist layer 62 is patterned on thesubstrate 40 for defining shallow trench isolations in the array area Iand the support area II. Next, using the first photoresist layer 62 as amask, the exposed portions of the pad layer 41 and the semiconductorsilicon substrate 40 are removed to form shallow trenches 63, as shownin FIG. 7C, thus defining an active area AA within the array area I.Then, the ARC layer 60 and the first photoresist layer 62 are removed.

In FIG. 7D, a nitride liner 64 is conformally deposited on the substrate40, and then a first HDP (high density plasma) oxide layer 66 is formedto fill the shallow trenches 63. Next, chemical mechanical polishing(CMP) is used to level off the top surfaces of the first HDP oxide layer66 and the nitride liner 64. Next, in FIG. 7E, a second photoresistlayer 68 is provided to cover the support area II. Next, using thenitride liner 64 as an etching stop layer, the first HDP oxide layer 66within the array area I is removed. Then, the second photoresist layer68 is removed. In FIG. 7F, after removing the nitride liner 64 and thepad layer 41, a sacrificial oxide layer is formed so as to perform anion implantation process on the array area I and the support area II foradjusting device threshold voltage.

In FIG. 7G, after removing the sacrificial oxide layer, a thermaloxidation process is employed to grow a gate oxide layer 70 on theexposed silicon surface of the substrate 40. Next, in FIG. 7H, a gatepolysilicon layer 72, a metallic silicide layer 74 (such as a WSi layer)and a nitride cap layer 76 are successively deposited on the substrate40. Then, using a third photoresist layer 78 as a mask to perform anetching process, the gate polysilicon layer 72, the metallic silicidelayer 74 and the nitride cap layer 76 within the array area I arepatterned as a gate conductive line GC, which partially overlaps twotops of two adjacent deep trenches DT.

In FIG. 7I, after removing the third photoresist layer 78, a second HDPoxide layer 80 is formed to fill the shallow trench 63 outside theactive area AA of the array area I, and then CMP is employed to leveloff the top surfaces of the second HDP oxide layer 80 and the gateconductive line GC. Next, in FIG. 7J, by performing photolithography andetching on the active area AA of the array area I, a first contact hole82I is formed to penetrate the gate conductive line GC and the gateoxide layer 70, thus exposing the substrate 40.

In FIG. 7K, a nitride spacer 84 is formed on the sidewall of the firstcontact hole 82I, and then an ion implantation process is performed toform a source/drain diffusion region 86 in the semiconductor siliconsubstrate 40 exposed by the first contact hole 82I. Next, deposition andCMP for a BPSG layer 88 and deposition and annealing for a TEOS oxidelayer 90 are successively performed thereon. Next, usingphotolithography and etching, a second contact hole 821I is formed toexpose the first contact hole 82I and the source/drain diffusion region86. Finally, in FIG. 7L, the second contact hole 821I is filled with apolysilicon contact layer 92, and then a W/TiN/Ti layer 94 is formed onthe polysilicon contact layer 92, and then a bitline 96 is patternedthereon.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A dynamic random access memory cell layout, comprising: a first gateconductor pair and a second gate conductor pair extending along a firstdirection, in which each gate conductor pair comprises a first gateconductive line and a second gate conductive line; a bitline pairextending along a second direction and intersecting the gate conductorpairs, in which the bitline pair comprises a first bitline and a secondbitline; a first active area extending along the second direction,crossing the first gate conductor pair and corresponding to the firstbitline; and a second active area extending along the second direction,crossing the second gate conductor pair and corresponding to the secondbitline; wherein, each active area comprises: a first deep trench and asecond deep trench formed in a substrate underneath the first gateconductive line and the second gate conductive line, respectively; abitline contact formed between the first gate conductive line and thesecond gate conductive line, in which the bitline contact iselectrically connected to the corresponding bitline; a commonsource/drain region formed in the substrate between the first gateconductive line and the second gate conductive line, in which the commonsource/drain region is electrically connected to the bitline contact; afirst vertical transistor formed overlying the first deep trench, inwhich the first vertical transistor comprises a first buried strapout-diffusion region formed in the substrate adjacent to one sidewall ofthe first deep trench; and a second vertical transistor formed overlyingthe second deep trench, in which the second vertical transistorcomprises a second buried strap out-diffusion region formed in thesubstrate adjacent to one sidewall of the second deep trench.
 2. Thedynamic random access memory cell layout as claimed in claim 1, whereinthe first deep trench is partially overlapped with the first verticaltransistor, and the sidewall profile of the first deep trench on theoverlapping portion is a line shape.
 3. The dynamic random access memorycell layout as claimed in claim 1, wherein the second deep trench ispartially overlapped with the second vertical transistor, and thesidewall profile of the second deep trench on the overlapping portion isa line shape.
 4. The dynamic random access memory cell layout as claimedin claim 1, wherein the first deep trench is partially overlapped withthe first vertical transistor, and the sidewall profile of the firstdeep trench on the overlapping portion comprises at least three edges.5. The dynamic random access memory cell layout as claimed in claim 4,wherein the sidewall of the first deep trench on the overlapping portionis a

-shaped profile.
 6. The dynamic random access memory cell layout asclaimed in claim 1, wherein the second deep trench is partiallyoverlapped with the second vertical transistor, and the sidewall profileof the second deep trench on the overlapping portion comprises at leastthree edges.
 7. The dynamic random access memory cell layout as claimedin claim 6, wherein the sidewall of the second deep trench on theoverlapping portion is a

-shaped profile.
 8. The dynamic random access memory cell layout asclaimed in claim 1, further comprising a first deep trench capacitorformed at the lower portion of the first deep trench.
 9. The dynamicrandom access memory cell layout as claimed in claim 1, furthercomprising a second deep trench capacitor formed at the lower portion ofthe second deep trench.
 10. A fabrication method for a dynamic randomaccess memory cell layout, comprising the steps of: providing asemiconductor silicon substrate having an array area and a support area;forming a pad layer overlying the semiconductor silicon substrate, inwhich the pad layer comprises a predetermined deep trench pattern;forming a first deep trench and a second deep trench in thesemiconductor silicon substrate within the array area; forming a firstdeep trench capacitor and a second deep trench capacitor at the lowerportions of the first deep trench and the second deep trench,respectively; forming a collar dielectric layer on the sidewalls of thefirst deep trench and the second deep trench, respectively, in which thecollar dielectric layer is disposed over the first deep trench capacitorand the second deep trench capacitor; forming a polysilicon layer in thefirst deep trench and the second deep trench, in which the polysiliconlayer is surrounded by the collar dielectric layer; forming a firstburied strap out-diffusion region and a second buried strapout-diffusion region in the semiconductor silicon substrate adjacent tothe sidewalls of the first deep trench and the second deep trench,respectively, in which the first buried strap out-diffusion region andthe second buried strap out-diffusion region are adjacent to thepolysilicon layer in the first deep trench and the second deep trench,respectively; forming a top isolating layer to cover the top of thepolysilicon layer in the first deep trench and the second deep trench;forming two first shallow trenches in the semiconductor siliconsubstrate within the array area to separate the active area from otherareas, in which the first shallow trenches are outside the first deeptrench and the second deep trench is within the array area; forming asecond shallow trench in the semiconductor silicon substrate within thesupport area; forming a liner on the substrate; forming a firstisolating layer in the first shallow trenches and the second shallowtrench, in which the top of the first isolating layer is leveled offwith the top of the liner; forming a photoresist layer to cover thesupport area; removing the first isolating layer formed in the firstshallow trenches within the array area; removing the photoresist layer,the exposed liner and the pad layer, in which the semiconductor siliconsubstrate within the active area of the array area protrude from the topisolating layer; forming a gate oxide layer on the exposed surface ofthe semiconductor silicon substrate; forming a gate conductive structureon the active area between the first deep trench and the second deeptrench; forming a second isolating layer to fill the first shallowtrenches, in which the top of the second isolating layer is leveled withthe top of the gate conductive structure; and forming a first contacthole penetrating the gate conductive structure and the gate oxide layerto expose the semiconductor silicon substrate.
 11. The fabricationmethod for a dynamic random access memory cell layout as claimed inclaim 10, further comprising the steps of: forming a spacer on thesidewall of the first contact hole; forming a common source/draindiffusion region in the semiconductor substrate exposed within the firstcontact hole; forming a first inter-layered dielectric and a secondinter-layered dielectric overlying the semiconductor silicon substrate;forming a second contact hole which penetrates the second inter-layereddielectric and the first inter-layered dielectric to expose the firstcontact hole and the common source/drain diffusion region; forming acontact layer in the second contact hole; and forming a bitlineoverlying the second inter-layered dielectric, in which the bitline iselectrically connected to the contact layer.
 12. The fabrication methodfor a dynamic random access memory cell layout as claimed in claim 10,wherein the liner is a silicon nitride layer.
 13. The fabrication methodfor a dynamic random access memory cell layout as claimed in claim 10,wherein the first isolating layer is a HDP (high-density plasma) oxidelayer.
 14. The fabrication method for a dynamic random access memorycell layout as claimed in claim 10, wherein the gate conductivestructure comprises a polysilicon layer, a metallic silicide layer and anitride cap layer.
 15. The fabrication method for a dynamic randomaccess memory cell layout as claimed in claim 10, wherein the secondisolating layer is a HDP (high-density plasma) oxide layer.
 16. Thefabrication method for a dynamic random access memory cell layout asclaimed in claim 11, wherein the spacer is a silicon nitride layer. 17.The fabrication method for a dynamic random access memory cell layout asclaimed in claim 11, wherein the first inter-layered dielectric is aBPSG layer.
 18. The fabrication method for a dynamic random accessmemory cell layout as claimed in claim 11, wherein the secondinter-layered dielectric is a TEOS oxide layer.